An edition of Formal specification and verification in VLSI design (1990)

Formal specification and verification in VLSI design

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Cover of: Formal specification and verification in VLSI design by Bruce S. Davie
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Last edited by ImportBot
February 25, 2022 | History
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An edition of Formal specification and verification in VLSI design (1990)

Formal specification and verification in VLSI design

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Publish Date
Publisher
Edinburgh University Press
Language
English
Pages
195

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Subjects
Integrated circuits, Very large scale integration, Computer-aided design, Verification, Integrated circuits, very large scale integration
Edition Availability
Cover of: Formal specification and verification in VLSI design
Formal specification and verification in VLSI design
1990, Edinburgh University Press
in English
  • Not in Library
Libraries near you: WorldCat

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Book Details

Edition Notes

Includes bibliographical references (p. 184-193) and index.

Published in
Edinburgh
Series
Edinburgh information technology series ;, 8

Classifications

Dewey Decimal Class
621.39/5
Library of Congress
TK7874 .D39 1990, TK7888.3

The Physical Object

Pagination
ix, 195 p. :
Number of pages
195

ID Numbers

Open Library
OL1636657M
ISBN 10
0748601597
LCCN
91188267
Goodreads
2397061

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History

Download catalog record: RDF / JSON
February 25, 2022 Edited by ImportBot import existing book
April 28, 2010 Edited by Open Library Bot Linked existing covers to the work.
February 1, 2010 Edited by WorkBot add more information to works
December 9, 2009 Created by WorkBot add works page