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This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.
- Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.
- Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.
- Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.
- Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.
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Previews available in: English
Edition | Availability |
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1
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Dec 16, 2014, Springer
paperback
1489986960 9781489986962
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Libraries near you:
WorldCat
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2
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
2013, Springer New York, Imprint: Springer
electronic resource /
in English
1441995420 9781441995421
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aaaa
Libraries near you:
WorldCat
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3
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Nov 25, 2012, Springer
paperback
1441995439 9781441995438
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zzzz
Libraries near you:
WorldCat
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Book Details
Published in
New York, NY
Table of Contents
Regular vs Irregular TSV Placementfor 3D IC
Steiner Routingfor 3D IC
Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC
Power Delivery Network Design for 3D IC
3D Clock Routing for Pre-bond Testability
TSV-to-TSV Coupling Analysis and Optimization
TSV Current Crowding and Power Integrity
Modeling of Atomic Concentration at the Wire-to-TSV Interface
Multi-Objective Archetectural Floorplanning for 3D IC
Thermal-aware Gate-level Placement for 3D IC
3D IC Cooling with Micro-Fluidic Channels
Mechanical Reliability Analysis and Optimization for 3D IC
Impact of Mechanical Stress on Timing Variation for 3D IC
Chip/Package Co-Analysis of Mechanical Stress for 3D IC
3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations
TSV Interfracial Crack Analysis and Optimization
Ultra High Logic Designs Using Monolithic 3D Integration
Impact of TSV Scaling on 3D IC Design Quality
3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.
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